Gearbox: modified, refer to #14

Prevents warnings (and more?) about CB being driven without a clock buffer.

m-labs/misoc#74

* 33 MHz CCLK
* QSPI
* compress
* CFGBVS
* CONFIG_VOLTAGE

Migen automatically renames some clock domains (for example in the case of
multiple modules defining a clock domain with the same name). When designing,
we need in some cases to know the final name of the clock domain and displaying
the list of avalaible clock domains helps figuring out what it is.

We are using Exception instead of KeyError since KeyError is not able to display
on multiple lines.

They are pretty big and post-route is usually interesting enough.
People can also use post-route to add their own checkpoints.

also remove some whitespace

* build an easy way for toggling cs to determine HMC830 SPI mode
* no miso contention as HMC7043 is three-wire

Improves TX data eye from 0.5ns to 1.5ns.

* Clock groups to designate asynchronous clocks is the recommended
way (ug903).
* This now includes generated clocks (!). And clock groups are
bidirectional.
* Don't bother creating boolean properties. The design checkpoints don't
have them which makes using the latter very hard. String properties are
allowed automatically and work fine also in checkpoints.
* Use pins to constrain the AsyncResetSynchronizers more precisely.

When targeting CPLD devices, Quartus generates the bitstream as a POF
file instead of SOF. It is not necessary to convert it to RBF bitstream
format in that case.

Signed-off-by: Pierre Surply <pierre.surply@lse.epita.fr>